supertile

Supertile definition for FPGA fabric.

This module contains the SuperTile class, which represents a composite tile made up of multiple smaller, individual tiles. Supertiles allow for the creation of more larger, complex and hierarchical structures within the FPGA fabric, combining different functionalities into a single, reusable block.

Classes

SuperTile

Store the information about a super tile.

Module Contents

SuperTile

class SuperTile

Store the information about a super tile.

Variables:

• name (str) – The name of the super tile.

• tileDir (Path) – Path to the tile directory.

• tiles (list[Tile]) – The list of tiles that make up the super tile.

• tileMap (list[list[Tile]]) – The map of the tiles that make up the super tile

• bels (list[Bel]) – The list of bels of that the super tile contains

• withUserCLK (bool) – Whether the super tile has a userCLK port. Default is False.

Properties

property max_height: int

Return the maximum height of the supertile.

property max_width: int

Return the maximum width of the supertile.

Methods

getInternalConnections() → list[tuple[list[Port], int, int]]

Return all the internal connections of the supertile.

Returns:

A list of tuples which contains the internal connected port and the x and y coordinate of the tile.

getPortsAroundTile() → dict[str, list[list[Port]]]

Return all the ports that are around the supertile.

The dictionary key is the location of where the tile is located in the supertile map with the format of “X{x}Y{y}”, where x is the x coordinate of the tile and y is the y coordinate of the tile. The top left tile will have key “00”.

Returns:

The dictionary of the ports around the super tile.

get_min_die_area(x_pitch, y_pitch, x_pin_thickness_mult=Decimal(1), y_pin_thickness_mult=Decimal(1), edge_offset=2) → tuple[Decimal, Decimal]

Calculate minimum SuperTile dimensions based on IO pin track requirements.

Takes the maximum per-side IO pin count across all constituent subtiles as a conservative upper bound, then derives the minimum physical width and height required.

See Tile.get_min_die_area for the track-based derivation.

Parameters:

• x_pitch (Decimal) – Vertical-layer track pitch (for north/south pins).

• y_pitch (Decimal) – Horizontal-layer track pitch (for east/west pins).

• x_pin_thickness_mult (Decimal) – Number of tracks each north/south pin spans, by default 1.

• y_pin_thickness_mult (Decimal) – Number of tracks each east/west pin spans, by default 1.

• edge_offset (int, optional) – Reserved tracks at tile edge, by default 2.

Returns:

(min_width, min_height)