tile

Tile class definition for FPGA fabric representation.

Classes

Tile

Store information about a tile.

Module Contents

Tile

class Tile(name, ports, bels, tileDir, matrixDir, gen_ios, userCLK, configBit=0, pinOrderConfig=None)[source]

Store information about a tile.

Parameters:

  • name (str) – The name of the tile

  • ports (list[Port]) – List of ports for the tile

  • bels (list[Bel]) – List of Basic Elements of Logic (BELs) in the tile

  • tileDir (Path) – Directory path for the tile

  • matrixDir (Path) – Directory path for the tile matrix

  • gen_ios (list[Gen_IO]) – List of general I/O components

  • userCLK (bool) – True if the tile uses a clk signal

  • configBit (int, optional) – Number of configuration bits for the switch matrix. Default is 0.

  • pinOrderConfig (dict[Side, PinOrderConfig] | None, optional) – Configuration for pin ordering on each side of the tile. If None, defaults to BUS_MAJOR sorting on all sides.

Variables:

  • name (str) – The name of the tile

  • portsInfo (list[Port]) – The list of ports of the tile

  • bels (list[Bel]) – The list of BELs of the tile

  • matrixDir (Path) – The directory of the tile matrix

  • matrixConfigBits (int) – The number of config bits the tile switch matrix has

  • gen_ios (list[Gen_IO]) – The list of GEN_IOs of the tile

  • withUserCLK (bool) – Whether the tile has a userCLK port. Default is False.

  • wireList (list[Wire]) – The list of wires of the tile

  • tileDir (Path) – The path to the tile folder

  • partOfSuperTile (bool, optional) – Whether the tile is part of a super tile. Default is False.

  • pinOrderConfig (dict, optional) – Configuration for pin ordering on each side of the tile.

Properties

property globalConfigBits: int[source]

Get the total number of global configuration bits.

Calculates the sum of switch matrix configuration bits and all BEL configuration bits.

Methods

getEastPorts(io) → list[Port][source]

Get all ports with east wire direction filtered by I/O type.

Parameters:

io (IO) – The I/O direction to filter by (INPUT or OUTPUT).

Returns:

List of east-direction ports with specified I/O type, excluding NULL ports.

getEastSidePorts() → list[Port][source]

Get all ports physically located on the east side of the tile.

Returns:

List of ports on the east side, excluding NULL ports.

getNorthPorts(io) → list[Port][source]

Get all ports with north wire direction filtered by I/O type.

Parameters:

io (IO) – The I/O direction to filter by (INPUT or OUTPUT).

Returns:

List of north-direction ports with specified I/O type, excluding NULL ports.

getNorthSidePorts() → list[Port][source]

Get all ports physically located on the north side of the tile.

Returns:

List of ports on the north side, excluding NULL ports.

getSouthPorts(io) → list[Port][source]

Get all ports with south wire direction filtered by I/O type.

Parameters:

io (IO) – The I/O direction to filter by (INPUT or OUTPUT).

Returns:

List of south-direction ports with specified I/O type, excluding NULL ports.

getSouthSidePorts() → list[Port][source]

Get all ports physically located on the south side of the tile.

Returns:

List of ports on the south side, excluding NULL ports.

getTileInputNames() → list[str][source]

Get all input port destination names for the tile.

Returns:

List of destination names for input ports, excluding NULL and JUMP direction ports.

getTileOutputNames() → list[str][source]

Get all output port source names for the tile.

Returns:

List of source names for output ports, excluding NULL and JUMP direction ports.

getWestPorts(io) → list[Port][source]

Get all ports with west wire direction filtered by I/O type.

Parameters:

io (IO) – The I/O direction to filter by (INPUT or OUTPUT).

Returns:

List of west-direction ports with specified I/O type, excluding NULL ports.

getWestSidePorts() → list[Port][source]

Get all ports physically located on the west side of the tile.

Returns:

List of ports on the west side, excluding NULL ports.

get_min_die_area(x_pitch, y_pitch, x_pin_thickness_mult=Decimal(1), y_pin_thickness_mult=Decimal(1), frame_data_width=32, frame_strobe_width=20, edge_offset=2) → tuple[Decimal, Decimal][source]

Calculate minimum tile dimensions based on IO pin track requirements.

The IO pin placer distributes pins across available tracks on each tile edge. Each pin occupies thickness_mult consecutive tracks, and edge_offset tracks are reserved at the start of the tile (see tile_io_place.allocate_tracks).

The minimum number of tracks on a side is therefore:

required_tracks = pin_count * thickness_mult + edge_offset

And the minimum physical dimension is:

min_dim = required_tracks * pitch
Parameters:

  • x_pitch (Decimal) – Vertical-layer track pitch (for north/south pins).

  • y_pitch (Decimal) – Horizontal-layer track pitch (for east/west pins).

  • x_pin_thickness_mult (Decimal) – Number of tracks each north/south pin spans, by default 1.

  • y_pin_thickness_mult (Decimal) – Number of tracks each east/west pin spans, by default 1.

  • frame_data_width (int, optional) – Frame data width, by default 32.

  • frame_strobe_width (int, optional) – Frame strobe width, by default 20.

  • edge_offset (int, optional) – Reserved tracks at tile edge, by default 2.

Returns:

(min_width, min_height)

get_port_count(side) → int[source]

Count total number of expanded physical pins on a given side of the tile.

Parameters:

side (Side) – The side of the tile to count ports for.

Returns:

Total number of expanded ports on the given side.