Interactive CLI Commands Reference

This is an auto-generated reference of all FABulous CLI commands available in interactive mode.

Setup

clone_tile

Clone a tile or supertile directory and register it in fabric.csv.

Copies the source tile directory to a new destination directory, renaming all files and replacing all internal references to match the new tile name. Also appends the required Tile/Supertile entries to fabric.csv.

install_FABulator

Download and install the latest version of FABulator.

Sets the the FABULATOR_ROOT environment variable in the .env file.

install_oss_cad_suite

Download and extract the latest OSS CAD suite.

The installation will set the FAB_OSS_CAD_SUITE environment variable in the .env file.

load_fabric

Load ‘fabric.csv’ file and generate an internal representation of the fabric.

Parse input arguments and set a few internal variables to assist fabric generation.

Fabric Flow

gen_all_tile

Generate all tiles by calling do_gen_tile.

gen_all_tile_macros

Generate GDSII files for all tiles in the fabric.

gen_bitStream_spec

Generate bitstream specification of the fabric.

By calling genBitStreamSpec and saving the specification to a binary and CSV file.

Also logs the paths of the output files.

gen_config_mem

Generate configuration memory of the given tile.

Parsing input arguments and calling genConfigMem.

Logs generation processes for each specified tile.

gen_fabric

Generate fabric based on the loaded fabric.

Calling gen_all_tile and genFabric.

Logs start and completion of fabric generation process.

gen_fabric_macro

Generate GDSII files for the entire fabric.

gen_geometry

Generate geometry of fabric for FABulator.

Checking if fabric is loaded, and calling ‘genGeometry’ and passing on padding value. Default padding is ‘8’.

Also logs geometry generation, the used padding value and any warning about faulty padding arguments, as well as errors if the fabric is not loaded or the padding is not within the valid range of 4 to 32.

gen_io_fabric

Generate I/O BELs for the entire fabric.

This command generates Input/Output Basic Elements of Logic (BELs) for all applicable tiles in the fabric, providing external connectivity across the entire FPGA design.

gen_io_pin_config

Generate an IO pin configuration YAML file for a tile or supertile.

gen_io_tiles

Generate I/O BELs for specified tiles.

This command generates Input/Output Basic Elements of Logic (BELs) for the specified tiles, enabling external connectivity for the FPGA fabric.

gen_model_npnr

Generate Nextpnr model of fabric.

By parsing various required files for place and route such as pips.txt, bel.txt, bel.v2.txt and template.pcf. Output files are written to the directory specified by metaDataDir within projectDir.

Logs output file directories.

gen_switch_matrix

Generate switch matrix of given tile.

Parsing input arguments and calling genSwitchMatrix.

Also logs generation process for each specified tile.

gen_tile

Generate given tile with switch matrix and configuration memory.

Parsing input arguments, call functions such as genSwitchMatrix and genConfigMem. Handle both regular tiles and super tiles with sub-tiles.

Also logs generation process for each specified tile and sub-tile.

gen_tile_macro

Generate GDSII files for a specific tile.

This command generates GDSII files for the specified tile, allowing for the physical representation of the tile to be created.

gen_top_wrapper

Generate top wrapper of the fabric by calling genTopWrapper.

run_FABulous_eFPGA_macro

Run the full FABulous eFPGA macro generation flow.

run_FABulous_fabric

Generate the fabric based on the CSV file.

Create bitstream specification of the fabric, top wrapper of the fabric, Nextpnr model of the fabric and geometry information of the fabric.

User Design Flow

gen_bitStream_binary

Generate bitstream of a given design.

deprecated: Use compile_design which includes bitstream generation.

gen_user_design_wrapper

Generate a user design wrapper for the specified user design.

This command creates a wrapper module that interfaces the user design with the FPGA fabric, handling signal connections and naming conventions.

place_and_route

Run place and route with Nextpnr for a given JSON file.

deprecated: Use compile_design --pnr-only instead.

run_FABulous_bitstream

Run FABulous to generate bitstream on a given design.

deprecated: Use compile_design instead.

run_simulation

Simulate given FPGA design.

Uses Taskfile.yml (preferred) or falls back to Make (deprecated). The bitstream_file argument should be a binary file generated by ‘gen_bitStream_binary’.

synthesis

Run Yosys synthesis for the specified Verilog files.

deprecated: Use compile_design --synth-only instead.

compile_design

Compile a user design through synthesis, PnR, and bitstream generation.

This function orchestrates the full compile flow by delegating to a compile Taskfile. It resolves input file paths, builds the synthesis command, and invokes the appropriate task(s) depending on the selected mode (full compile, synth-only, pnr-only, or no-bitgen).

Helper

GUI

start_FABulator

Start FABulator if an installation can be found.

If no installation can be found, a warning is produced.

Script

run_script

Execute script.

run_tcl

Execute TCL script relative to the project directory.

Specified by <tcl_scripts>. Use the ‘tk’ module to create TCL commands.

Also logs usage errors and file not found errors.

Tools

generate_custom_tile_config

Generate a custom tile configuration for a given tile folder.

Or path to bel folder. A tile .csv file and a switch matrix .list file will be generated.

The provided path may contain bel files, which will be included in the generated tile .csv file as well as the generated switch matrix .list file.

start_klayout_gui

Start OpenROAD GUI if an installation can be found.

If no installation can be found, a warning is produced.

start_openroad_gui

Start OpenROAD GUI if an installation can be found.

If no installation can be found, a warning is produced.

Other

exit

Exit the FABulous shell and log info message.

q

Exit the FABulous shell and log info message.

quit

Exit the FABulous shell and log info message.

Timing Characterization

timing_model

Generate a timing model for the fabric.

Timing information is extracted from the GDS layout and used to create a timing model compatible with nextpnr for timing-aware place and route. This command generates a timing model for the FPGA fabric based on the specified mode (physical or structural) and outputs it to a file named pips.txt in the .FABulous directory. If no config file is provided, the automated flow must be run first to generate post-layout files. If a config file is provided, it will be used for timing model generation instead of CLI arguments. This allows for more complex configurations like different PDK support. If emit-config-template is specified, a config template will be output and no timing model will be generated.